Examples of 'buffer memories' in a sentence
Meaning of "buffer memories"
buffer memories: Denotes the recollection of certain memories that act as a protective barrier or cushion against negative or distressing experiences
How to use "buffer memories" in a sentence
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buffer memories
These buffer memories are called concatenated data buffers.
This can be done by means of buffer memories.
Thus buffer memories can be disposed within the switching matrix.
The result of this function could then be stored in buffer memories.
The buffer memories are upstream and are not shown in this circuit.
Different values of control can then be memorised in the corresponding buffer memories.
The buffer memories are linked to one another for a selected socket.
The DRAMs are generally associated with processors and used as buffer memories.
The two buffer memories alternate between receiving and outputing data.
The reasons for blocking include congestion of the buffer memories in the switches.
Buffer memories for constituting these bursts are added to the interior of the circuit.
The pulses carry messages that have been received by the associated buffer memories.
The amount of memory required for the line buffer memories can therefore be reduced significantly.
These buffer memories will then play the two roles provided for in the invention.
But this solution obliges the DMA controller to manage an ordered list of buffer memories.
See also
Each of these buffer memories is accessible at a specific address through data bus D.
The particular addresses are, for example, boundary addresses of buffer memories intended for the transfer.
Secondly, the buffer memories are managed according to a sequencing by priorities.
This patent specification describes a method of mapping buffer memories realized in the form of fifo-memories.
This requires that the device stores the two half-cycles in the rotary buffer memories.
Data and address buffer memories associated with the memory ;.
Otherwise, storing said two half-cycles in the buffer memories.
Alternatively, some or all of the buffer memories may be separated in discrete memory elements.
On its 5 inputs a multiplexor 12 receives the output from the buffer memories.
In one embodiment, these three buffer memories can store up to ten consecutive half-cycles.
The buffer status array 23 records the status of each of the three shared buffer memories 19.
In other embodiments, two buffer memories can alternatively store successive pictures instead of picture fields.
Management means for the state of the buffer memories 11 ;.
The output buffer memories 24 are preferably FIFO memories.
FIG . 6 is an algorithm for scanning buffer memories in the collector ;.
Moreover, the buffer memories store control data output from the CPU 401 of the control section 4.
FIG . 2 represents in more detail the buffer memories of a conventional peer.
For 33 to 64 groups, two switches each equipped with two buffer memories are required.
The address bits AD 1 stored in the buffer memories 35 are applied to the decoder 7.
For 65 to 96 groups, three switches each equipped with three buffer memories are required.
For reasons of clarity, the content of the buffer memories is not represented in FIG . 2.
Two MACs, RBCs, DPCs, and buffer memories are used.
Likewise the display control circuit also has two buffer memories ( 66, 67 ) for the purpose described below.
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