Examples of 'buffer register' in a sentence
Meaning of "buffer register"
buffer register: In computing, a buffer register is a temporary storage area typically used to store data during the transfer of information between devices or processes
How to use "buffer register" in a sentence
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buffer register
Reset clears the transmitter buffer register to all zeros.
A third line buffer register makes it possible to overcome this problem.
This cell is not then transferred into the input buffer register rte.
The transmitter buffer register is loaded when these registers are written.
The last incoming byte will be kept in the Buffer Register for later use.
The input buffer register rte is connected to an input cell bus bce.
Just after this transfer a new packet is transferred from MRAM to the buffer register RTS.
Storage of the result in a buffer register for the considered output octet.
A buffer register receiving a first address corresponding to a selected frequency ;.
For this reason, only one buffer register is used at this point.
The results Kn are applied to the input of a third buffer register 9.
The samples are stored in a buffer register from which a word of fixed width is extracted.
The polar angle value Pn is transmitted downstream through a buffer register circuit 32.
The reading function of the buffer register is activated at least during the first cycle.
The MMU 4 supplies the physical address PA SRC to the buffer register 7 for storage.
See also
A receive buffer register connected to said receive deserializer;.
Assembly according to claim 6, wherein the buffer register comprises a single stage.
A second buffer register having d parallel inputs and d parallel outputs ;.
During a normal operating phase, the writing function of buffer register 5 is activated at each cycle.
The input of buffer register 5 is connected to the output of the associated latch 2 a.
A data bus for connecting the said input / output buffer register to the said data memory.
The second buffer register having d parallel inputs and d parallel outputs, and.
When the SPD is read, it is the receive buffer register that is actually read.
The buffer register R T 32 for which the digital contents initially correspond to the future analog value.
These words are written in a buffer register of the video generator 14.
The output of the adder 4 is connected to the input of the buffer register 6.
The states saved in buffer register 5 during this backup cycle can then be erroneous.
Assembly according to claim 6, wherein the buffer register comprises two stages.
The contents of the buffer register are transferred under the control of a local oscillator ( 10 ).
The parallel outputs of the generator 10 are connected to the parallel inputs of a buffer register 11.
According to the example taken, the buffer register 6 is initialized to 1.
The connection to the data bus 13 takes place through the outputs of the buffer register 11.
A variant consists of using a simple buffer register in place of register 123.
This buffer register has inputs 51, which are connected to bus B for receiving data.
The conductor 26 associated with the buffer register acts as a transfer gate.
The buffer register 7 is linked to the multiplexer 9 ′.
Thus q-dmin=1 and the last state saved in the buffer register will be erroneous.
According to a preferred embodiment, the buffer register 43 is a FIFO register comprising n locations of n bits.
Then the data therefrom is transmitted to and stored in the memory buffer register 104.
External material buffer register - - Optional.
The partial sum corresponding to filter FA is stored in buffer register 14.
The output circuit 14 comprises a buffer register preceding the output S1 of the enciphering unit.
Figure 4A is a simplified diagram of a buffer register unit ;.
In the case where r=1, buffer register 5 is then formed by a single latch.
The parallel outputs of the counter 70 are also connected to a buffer register 74.
FIG . 6 represents the first buffer register or input buffer register RTE.
This word is received by the interface circuit 54 and memorized in a buffer register 58.
Outputs 52 of this data reception buffer register 50 are connected to data inputs of receiving unit 4.
An input management logic circuit 38, associated with the input buffer register 36.
This bit is stored into a transmission buffer register ( BX ) 30.
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