Examples of 'instruction cache' in a sentence
Meaning of "instruction cache"
instruction cache is a type of cache memory used in computing systems to store copies of instructions for faster access and execution by the CPU
How to use "instruction cache" in a sentence
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instruction cache
A variant of prefetch for the instruction cache.
Coupled to the instruction cache is the instruction decode unit.
This gives significantly higher data and instruction cache locality.
Instruction cache memory.
The index is a portion of the instruction cache fetch address.
Instructions and predecode bits are stored in a cache line in ann instruction cache.
Primary instruction cache.
The instruction fetch mechanism preferably includes an instruction cache memory.
Inline code to invalidate instruction cache entries after setting up nested function trampolines.
Each thread shares a common data cache and a common instruction cache.
Some machines with longer instruction cache latencies would have an even larger loss.
The predecode unit predecodes the instructions prior to their storage within an instruction cache.
This might be compensated by savings in instruction cache and memory and instruction decoding circuits.
The instruction cache is only used for storing instructions and executes in a sequential manner.
The predecode information is written into the instruction cache along with the fetched instructions.
See also
Dynamic flow instruction cache memory organized around trace segments independent of virtual address line.
CPU cache memory is divided into an instruction cache and a data cache.
Instruction cache 30 is a high speed cache memory configured to store instruction blocks.
In stage one, four instructions are fetched from the instruction cache.
For example, the instruction cache checks to see if the instruction is present.
Bandwidth increase in branch prediction unit and level 1 instruction cache.
Can also cause an increase in instruction cache misses, which may adversely affect performance.
This second or further storage mechanism is represented by compound instruction cache 38.
During a fetch stage, the instruction cache 16 fetches a block of instructions.
Each instruction block is associated with a thread tag stored within instruction cache 30.
The instruction cache is direct-mapped and virtually indexed, physically tagged.
The first level consists of two caches, an instruction cache and a data cache.
Additionally, instruction cache 30 may detect branches and perform branch prediction.
According to another embodiment, method of storing branch instructions into an instruction cache is disclosed.
The instruction decoder 18 and instruction cache 16 are coordinated by a protocol which will now be described.
We will describe a scalar processor wherein branch-prediction information is provided within an instruction cache memory.
The flow of instructions from the instruction cache 64 is indicated in FIG.
This allows full-speed operation with a much smaller cache than a traditional full-time instruction cache.
Then flushes TLB, instruction cache etc.
The predecode step stores predecode information along with the fetched instruction in the L1 instruction cache.
Prefetch / Fetch, Instructions are fetched from the instruction cache and aligned for decoding.
The floating-point instruction cache is also increased in capacity to 24 entries from 20.
Five processors share a 32 kB instruction cache.
The instruction cache 16 and instruction decoder 18, for dispatching instructions, form an instruction dispatch arrangement.
The interrupt service routine address is then conveyed to instruction cache 30.
Prior to executing the program, an instruction cache is invalidated in step 604.
These instructions and their tags are supplied to and stored into the compound instruction cache 412.
As will be noted, the instruction cache 16a is similar to the instruction cache 16 of Figure 2.
This instruction counter controls the fetching of the instructions from the compound instruction cache 412.
There is a 16KB instruction cache.
During the fetch stage, two instructions were fetched from a 16 KB direct-mapped instruction cache.
The instruction cache is external and supports a capacity of 256 KB to 4 MB.
Figure 2 is a detailed block diagram of the instruction cache of Figure 1 ;.
Next, at block 738, the sequencer aligns the double-word retrieved from the instruction cache.
A method of storing branch instructions into an instruction cache ( I-cache ) comprising,.
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